Paper Info
Title
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
Abstract
With technology scaling, the trend for high-performance integrated circuits is toward ever higher operating frequency, lower power supply voltages, and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the 2001 International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in application specific integrated circuit (ASIC)-like circuits. The problem is formulated as one of nonlinear optimization and is solved using a sensitivity-based quadratic programming (QP) solver. The adjoint sensitivity method is applied to calculate the first-order sensitivities. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change in the total chip area.
Year
DOI
Venue
2003
10.1109/TCAD.2003.809658
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
DocType
Volume
higher power dissipation,decap placement,automated placement,adjoint waveform,optimal decoupling capacitor sizing,power grid noise,lower power supply voltage,application specific integrated circuit,standard-cell layout design,adjoint sensitivity method,on-chip power grid,high-performance integrated circuit
Journal
22
Issue
ISSN
Citations 
4
0278-0070
64
PageRank 
References 
Authors
4.05
13
3
Name
Order
Citations
PageRank
Haihua Su140527.32
Sani R. Nassif22268247.45
S. R. Nassif335927.96