Name
Title | ||
|---|---|---|
Real-Time Chain-Structured Synchronous Dataflow: Latency and Data Memory Requirement Formal Determination |
Abstract | ||
|---|---|---|
In numerous computational applications in mechanics, in engineering, as well as, in financial issues, the ability of manipulating instantly the state vector from the input is more than significant. Thus, in this paper, we extend a method for the instantly ... |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ICAS.2009.27 | ICAS |
Keywords | DocType | Citations |
hardware,real time,schedules,digital signal processors,digital signal processing,input output,process design,scheduling algorithm,latency,scheduling,memory latency,digital signal processor,scheduling problem | Conference | 0 |
PageRank | References | Authors |
0.34 | 4 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hui Xue Zhao | 1 | 6 | 2.43 |
| Laurent George | 2 | 214 | 29.39 |
| Ivan Bourmeyster | 3 | 0 | 0.68 |
| Stephan Tassart | 4 | 2 | 1.07 |
| Laurent Said | 5 | 0 | 0.34 |