Title
Reducing energy consumption of parallel sparse matrix applications through integrated link/CPU voltage scaling
Abstract
Reducing power consumption is quickly becoming a first-class optimization metric for many high-performance parallel computing platforms. One of the techniques employed by many prior proposals along this direction is voltage scaling and past research used it on different components such as networks, CPUs, and memories. In contrast to most of the existent efforts on voltage scaling that target a single component (CPU, network or memory components), this paper proposes and experimentally evaluates a voltage/frequency scaling algorithm that considers CPU and communication links in a mesh network at the same time. More specifically, it scales voltages/frequencies of CPUs in the nodes and the communication links among them in a coordinated fashion (instead of one after another) such that energy savings are maximized without impacting execution time. Our experiments with several tree-based sparse matrix computations reveal that the proposed integrated voltage scaling approach is very effective in practice and brings 13% and 17% energy savings over the pure CPU and pure communication link voltage scaling schemes, respectively. The results also show that our savings are consistent with the different network sizes and different sets of voltage/frequency levels.
Year
DOI
Venue
2007
10.1007/s11227-007-0113-9
The Journal of Supercomputing
Keywords
DocType
Volume
Energy consumption,Dynamic voltage scaling,Parallel sparse matrix,Computation,Communication networks
Journal
41
Issue
ISSN
Citations 
3
0920-8542
6
PageRank 
References 
Authors
0.50
25
5
Name
Order
Citations
PageRank
Seung Woo Son129631.43
Konrad Malkowski2445.86
Guilin Chen39210.54
Mahmut T. Kandemir47371568.54
Padma Raghavan546077.54