Title
Using Reconfigurable Supercomputers and C-to-Hardware Synthesis for CNN Emulation
Abstract
The complexity of hardware design methodologies represents a significant difficulty for non hardware focused scientists working on CNN-based applications. An emerging generation of Electronic System Level (ESL) design tools is been developed, which allow software-hardware codesign and partitioning of complex algorithms from High Level Language (HLL) descriptions. These tools, together with High Performance Reconfigurable Computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of CNN-based applications. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, is analyzed. A sequential CNN architecture, suitable for FPGA implementation, proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results for a typical edge detection algorithm shown that, with a minimum development time, a 10x acceleration, when compared to the software emulation, can be obtained.
Year
DOI
Venue
2009
10.1007/978-3-642-02267-8_27
international work-conference on the interplay between natural and artificial computation
Keywords
Field
DocType
cnn-based application,article codeveloper,esl ide,cnn emulation,ds1002 hprc platform,application specific fpga chip,reconfigurable supercomputers,high level language,codeveloper tool,high performance reconfigurable computer,electronic system level,c-to-hardware synthesis,fpga implementation,edge detection,chip
Computer architecture,Computer science,Edge detection,Electronic system-level design and verification,Field-programmable gate array,Emulation,High-level programming language,Acceleration,Cellular neural network,Hardware emulation,Embedded system
Conference
Volume
ISSN
Citations 
5602
0302-9743
2
PageRank 
References 
Authors
0.46
10
4