Name
Abstract | ||
|---|---|---|
This paper presents an event-driven adaptive voltage scaling (AVS) system, where a vanguard collaborates with a rearguard to find a minimal supply voltage. While the vanguard is responsible for the slack cycle time estimation, the rearguard allows voltage over-scaling with a variable-latency datapath. An improved vanguard is proposed based on online static timing analysis (STA), which monitors a scalable number of critical path candidates at run time. In our simulations, the delay estimation error is within 10%, which is relatively small compared to critical path variations of prevailing multi-Vt designs in deep-submicron era. A testchip with a 32-bit tiny RISC has been fabricated with the TSMC 65nm LP process technology to demonstrate the effectiveness. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1785481.1785560 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
delay estimation error,improved vanguard,voltage over-scaling,critical path candidate,vanguard collaborates,slack cycle time estimation,critical path variation,minimal supply voltage,collaborative voltage scaling,variable-latency datapath,event-driven adaptive voltage scaling,online sta,run time,critical path,static timing analysis,cycle time | Datapath,Computer science,Latency (engineering),Voltage,Real-time computing,Electronic engineering,Rearguard,Vanguard,Static timing analysis,Critical path method,Scalability,Embedded system | Conference |
Citations | PageRank | References |
2 | 0.73 | 12 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tay-Jyi Lin | 1 | 139 | 24.36 |
| Pi-Cheng Hsiao | 2 | 2 | 0.73 |
| Chi-Hung Lin | 3 | 217 | 34.67 |
| Shu-chang Kuo | 4 | 5 | 1.58 |
| Chou-Kun Lin | 5 | 6 | 1.56 |
| Yu-Ting Kuo | 6 | 60 | 9.60 |
| Chih-Wei Liu | 7 | 158 | 27.02 |
| Yuan-Hua Chu | 8 | 99 | 38.56 |