Name
Abstract | ||
|---|---|---|
Power consumption of high-speed low-resolution analog-to-digital converters (ADCs) can be reduced by means of calibration. However, this solution has some drawbacks such as time slot allocation for calibration and die area increase. This paper presents a 5-bit 1-Gs/s ADC without calibration, fabricated in 90-nm CMOS. Low power consumption has been ensured by operating at both architecture and comp... |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TIM.2013.2278998 | IEEE Transactions on Instrumentation and Measurement |
Keywords | Field | DocType |
Transistors,Latches,Calibration,Clocks,Interpolation,Capacitance,Power demand | Analog multiplier,Comparator,Effective resolution bandwidth,Sampling (signal processing),CMOS,Electronic engineering,Effective number of bits,Successive approximation ADC,Mathematics,Low-power electronics | Journal |
Volume | Issue | ISSN |
63 | 2 | 0018-9456 |
Citations | PageRank | References |
3 | 0.40 | 10 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stefano D'Amico | 1 | 129 | 27.42 |
| Giuseppe Cocciolo | 2 | 5 | 3.69 |
| Annachiara Spagnolo | 3 | 9 | 3.05 |
| Marcello De Matteis | 4 | 42 | 17.29 |
| Andrea Baschirotto | 5 | 168 | 48.21 |