Name
Abstract | ||
|---|---|---|
This paper presented a latency and power model to determine the bus configuration of a target SoC system at its early design stage. The latency model analyzed the latencies of an on-chip bus and provided throughput reflecting the bus configuration. The power model provided power estimation based on the pre-determined bus architecture. This paper showed new parameters to devise the proposed models such as bus usage, active bridge ratio, etc. Moreover, we evaluated the throughput of the bus and compared this with the required throughput of the target SoC, including a number of real IPs. This target SoC was configured based on the estimation results obtained from the proposed bus model. This estimation were compared with the simulation results of target SoC design for verifying the accuracy of the proposed model. The evaluation showed that the accuracies of the proposed model for the latency and the power model were over 85% and 92%, respectively. This result set the standard for an efficient bus structure for a SoC design. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1007/978-3-540-73625-7_22 | SAMOS |
Keywords | Field | DocType |
power model,on-chip bus modeling,efficient bus structure,latency model,on-chip bus,bus usage,target soc,bus configuration,performance estimation,proposed bus model,pre-determined bus architecture | Result set,IEBus,Latency (engineering),Computer science,Performance estimation,Power model,Local bus,Throughput,Embedded system | Conference |
Volume | ISSN | ISBN |
4599 | 0302-9743 | 3-540-73622-0 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jehoon Lee | 1 | 37 | 9.61 |
| Young-Shin Cho | 2 | 0 | 0.34 |
| Seok-Man Kim | 3 | 0 | 1.01 |
| Kyoung-Rok Cho | 4 | 217 | 31.77 |