Abstract | ||
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New results are given concerning the design of combinational logic circuits. We give time and component bounds for combinational circuits specified in several ways. For any sequential machine defined by linear recurrence relations, we discuss an algorithm for the synthesis of equivalent combinational logic. The procedure includes upper bounds on the time and components involved. We also discuss the transformation of nonlinear recurrences into combinational circuits. Examples are given using gates as well as IC's as components. These include binary addition, multiplication, and ones' position counting. The time and component bounds our procedure yields compare favorably with traditional results. |
Year | DOI | Venue |
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1977 | 10.1109/TC.1977.1674909 | IEEE Transactions on Computers |
Keywords | DocType | Volume |
linear recurrence relation,binary addition,nonlinear recurrence,combinational circuit synthesis,new result,component bounds,position counting,equivalent combinational logic,component bound,procedure yield,combinational logic circuit,combinational circuit,combinational circuits,sequential circuits | Journal | C-26 |
Issue | ISSN | Citations |
8 | 0018-9340 | 6 |
PageRank | References | Authors |
4.00 | 10 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Shyh-Ching Chen | 1 | 295 | 260.23 |
D. J. Kuck | 2 | 6 | 4.00 |