Name
Title | ||
|---|---|---|
Reusability-aware cache memory sharing for chip multiprocessors with private L2 caches |
Abstract | ||
|---|---|---|
In this paper, we propose a novel on-chip L2 cache organization for chip multiprocessors (CMPs) with private L2 caches. The proposed approach, called reusability-aware cache sharing (RACS), combines the advantages of both a private L2 cache and a shared L2 cache. Since a private L2 cache organization has a short access latency, the RACS scheme employs a private L2 cache organization. However, when a cache block in a private L2 cache is selected for eviction, RACS first evaluates its reusability. If the block is likely to be reused in the near future, it may be saved to a peer L2 cache which has space available. In this way, the RACS scheme effectively simulates the larger capacity of a shared L2 cache. Simulation results show that RACS reduced the number of off-chip memory accesses by 24% compared to a pure private L2 cache organization on average for the SPLASH 2 multi-threaded benchmarks, and by 16% for multi-programmed benchmarks. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1016/j.sysarc.2009.09.003 | Journal of Systems Architecture - Embedded Systems Design |
Keywords | Field | DocType |
reusability-aware cache sharing,chip multiprocessors,cache block,cmps,private l2 cache,multi-threaded benchmarks,cache management,multi-programmed benchmarks,reusability,reusability-aware cache memory sharing,novel on-chip l2 cache,larger capacity,racs scheme,l2 cache,l2 cache organization,chip,cache memory | Cache invalidation,Cache pollution,Computer science,Cache,Parallel computing,Real-time computing,Cache algorithms,Page cache,Cache coloring,Bus sniffing,Smart Cache | Journal |
Volume | Issue | ISSN |
55 | 10-12 | Journal of Systems Architecture |
Citations | PageRank | References |
1 | 0.35 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyunhee Kim | 1 | 34 | 5.51 |
| Sungjun Youn | 2 | 1 | 0.69 |
| Jihong Kim | 3 | 1336 | 104.37 |