Name
Abstract | ||
|---|---|---|
The impedance of a microprocessor power-delivery network peaks at ~140MHz, resulting in power-grid resonance, which lowers operating frequency and compromises reliability. A suppression circuit uses an active-damping technique with a maximum of 12.7dB peak-to-peak noise reduction from 70 to 250MHz in a 90nm CMOS process. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISSCC.2007.373406 | ISSCC |
Keywords | Field | DocType |
cmos process,cmos integrated circuits,90 nm,on-die supply-resonance suppression circuit,microprocessor chips,power supply circuits,power-grid resonance,microprocessor power-delivery network,70 to 250 mhz,noise reduction,active damping,damping | Noise reduction,Operating frequency,Computer science,Microprocessor,Electronic engineering,CMOS,Cmos process,Electrical impedance,Electrical engineering,Resonance | Conference |
Volume | Issue | ISSN |
null | null | 0193-6530 E-ISBN : 1-4244-0853-9 |
ISBN | Citations | PageRank |
1-4244-0853-9 | 25 | 3.25 |
References | Authors | |
0 | 11 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jianping Xu | 1 | 25 | 3.25 |
| Peter Hazucha | 2 | 225 | 28.53 |
| Mingwei Huang | 3 | 25 | 3.25 |
| Paolo A. Aseron | 4 | 218 | 18.44 |
| Fabrice Paillet | 5 | 63 | 12.48 |
| Gerhard Schrom | 6 | 109 | 20.56 |
| James Tschanz | 7 | 963 | 121.38 |
| Cangsang Zhao | 8 | 27 | 3.69 |
| Vivek De | 9 | 3024 | 577.83 |
| Tanay Karnik | 10 | 1623 | 182.57 |
| Greg Taylor | 11 | 50 | 10.44 |