Name
Abstract | ||
|---|---|---|
H.264-AVC is one of the most popular formats for the recording, compression and distribution of video. Encoders and decoders for the H.264 standard are widely in demand, and efficient strategies for enhancing their performance have been areas of active research. With the proliferation of many-core architectures in the embedded community, there has been a trend towards parallelizing implementations of encoders and decoders. In this paper, we present a run time heuristic which exploits macro-block level parallelism and efficient scheduling inside a H.264 decoder to reduce the number of cache misses and improve the processor utilization. Experiments on standard benchmarks show a significant speed-up over contemporary strategies proposed in literature. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1007/978-3-642-42024-5_24 | Communications in Computer and Information Science |
Field | DocType | Volume |
Heuristic,Computer architecture,Multi processor,Cache,Computer science,Scheduling (computing),Parallel computing,Exploit,Implementation,Encoder,Decoding methods | Conference | 382 |
ISSN | Citations | PageRank |
1865-0929 | 1 | 0.36 |
References | Authors | |
2 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arani Bhattacharya | 1 | 21 | 7.10 |
| Ansuman Banerjee | 2 | 170 | 41.69 |
| Susmita Sur-Kolay | 3 | 333 | 39.50 |
| Prasenjit Basu | 4 | 33 | 4.83 |
| Bhaskar J. Karmakar | 5 | 2 | 0.79 |