Name
Title | ||
|---|---|---|
Efficient Modeling of Itanium Architecture during Instruction Scheduling using Extended Finite State Automata |
Abstract | ||
|---|---|---|
Effective and efficient modeling and management of hardware resources have always been critical toward generating highly efficient code in optimizing compilers. The instruction templates and dispersal rules of the Itanium® architecture add new complexity in managing resource constraints to instruction scheduler. We extended a finite state automaton (FSA) approach to efficiently manage all key resource constraints of an Itanium® architecture on-the-fly during instruction scheduling. We have fully integrated the FSA-based resource management into the instruction scheduler in the Open Research Compiler for the Itanium® architecture. Our integrated approach shows up to 12% speedup on some SPECint2000 benchmarks and 4.5% speedup on average for all SPECint2000 benchmarks on an Itanium®-based system when compares to an instruction scheduler with decoupled resource management. In the meantime, the instruction scheduling time of our approach is reduced by 4% on average. |
Year | Venue | Keywords |
|---|---|---|
2004 | J. Instruction-Level Parallelism | finite state automata,optimizing compiler,finite state automaton,instruction scheduling,resource manager |
Field | DocType | Volume |
Resource management,Architecture,Computer architecture,Explicitly parallel instruction computing,Instruction scheduling,Computer science,Parallel computing,Itanium,Real-time computing,Compiler,Finite-state machine,Speedup | Journal | 6 |
Citations | PageRank | References |
0 | 0.34 | 12 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dong-yuan Chen | 1 | 107 | 10.04 |
| Lixia Liu | 2 | 2 | 0.79 |
| Roy Dz-ching Ju | 3 | 326 | 21.37 |
| Feng Chen | 4 | 218 | 46.85 |
| Shuxin Yang | 5 | 16 | 2.59 |
| Chengyong Wu | 6 | 515 | 26.67 |