Name
Abstract | ||
|---|---|---|
In this paper, the VLSI implementation of a real-time EZW video coder is presented. The proposed architecture adopts a modified 2-D DWT subband decomposition scheme, with the purpose of reducing the transposition memory requirements of 2-D DWT. In addition, through the use of a parallelized partial zerotree EZW scheme, temporary buffer requirements between the DWT and EZW modules are also reduced. The video encoder is integrated in a 0.35 um 3LM chip by using 341 K transistors on a 4.93 x 4.93 mm2 die. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1145/370155.370211 | ASP-DAC |
Keywords | Field | DocType |
2-d dwt,mm2 die,parallelized partial zerotree ezw,reduced memory accessing,real-time ezw video coder,realtime wavelet video coder,2-d dwt subband decomposition,video encoder,vlsi implementation,proposed architecture,k transistor,ezw module,very large scale integration,throughput,vlsi,encoding,frequency,pixel,real time systems,chip,video compression,real time | Computer science,CMOS,Real-time computing,Electronic engineering,Pixel,Encoder,Throughput,Data compression,Very-large-scale integration,Encoding (memory),Embedded system,Wavelet | Conference |
ISBN | Citations | PageRank |
0-7803-6634-4 | 2 | 0.43 |
References | Authors | |
2 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Roberto Y. Omaki | 1 | 3 | 1.15 |
| Yu Dong | 2 | 2 | 0.43 |
| Morgan H. Miki | 3 | 4 | 1.05 |
| Makoto Furuie | 4 | 2 | 0.77 |
| Daisuke Taki | 5 | 2 | 0.77 |
| Masaya Tarui | 6 | 2 | 0.77 |
| Gen Fujita | 7 | 25 | 5.17 |
| Takao Onoye | 8 | 329 | 68.21 |
| Isao Shirakawa | 9 | 220 | 65.34 |