Name
Abstract | ||
|---|---|---|
This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLL's second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response and achieves fast settling. Unlike the previously-reported peaking-free PLLs the proposed PLL implements the peaking-free loop filter directly in digital domain without requiring additional components. A time-to-digital converter (TDC) is implemented as a set of three binary phase-frequency detectors that oversample the timing error with time-varying offsets achieving a linear TDC gain and PLL bandwidth insensitive to the jitter condition. And a 9.2-GHz digitally-controlled LC oscillator (DCO) with transformer-based tuning realizes a predictable DCO gain set by a ratio between two digitally-controlled currents. The prototype 9.2-GHz-output digital PLL fabricated in a 65nm CMOS demonstrates a fast settling time of 1.58-μs with 690-kHz bandwidth. The PLL has a 3.477-psrms divided clock jitter and -120dBc/Hz phase noise at 10MHz offset while dissipating 63.9-mW at a 1.2-V supply. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/JSSC.2014.2312412 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
digital loop filter,peaking free transfer function,time-digital converter,digital loop filter (dlf),cmos,power 63.9 mw,delta-sigma modulator (dsm),digital phase locked loop,voltage 1.2 v,binary phase-frequency detectors,low-power linear time-to-digital converter,size 65 nm,digital phase locked loops,delta-sigma modulator,hardware complexity,frequency 700 khz,circuit components,closed-loop zero,binary phase-frequency detector,dco,digitally controlled oscillator,field effect mmic,time-to-digital converter (tdc),second order transfer function,digital pll,pll,digitally controlled lc oscillator,microwave oscillators,delta-sigma modulation,digitally controlled currents,cmos integrated circuits,clocks,phase locked loops,timing jitter,digital filters,transformer-tuned lc oscillator,timing error,optimal loop filter,cmos integrated circuit,closed-loop transfer function,digital phase-locked loop (dpll),time-digital conversion,cmos digital integrated circuits,peaking-free jitter transfer function,loop dynamics,peaking-free loop filter,digital phase-locked loop,oscillators,phase interpolators,peaking-free transfer function,lc circuits,clock jitter,digital control,digitally controlled oscillator (dco),frequency 9.2 ghz,tdc | Conference | 49 |
Issue | ISSN | Citations |
8 | 0018-9200 | 1 |
PageRank | References | Authors |
0.38 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sigang Ryu | 1 | 2 | 2.21 |
| Hwanseok Yeo | 2 | 6 | 2.30 |
| Yoontaek Lee | 3 | 2 | 1.41 |
| Seuk Son | 4 | 11 | 2.98 |
| Jaeha Kim | 5 | 382 | 51.63 |