Name
Abstract | ||
|---|---|---|
We present the cycle-time aware architecture synthesis methodology used in PICO-NPA that automatically synthesizes minimal cost RT-level designs from high-level specifications to meet a given cycle-time. This allows subsequent physical synthesis to succeed on first pass with predictable performance. The core of the methodology is a static timing analysis engine that is used at multiple levels - program-level, architecture-level and RT-level - in order to identify, schedule and validate useful operator chains that are incorporated into the design automatically. We present architecture synthesis results for several embedded applications and evaluate the benefits of this technique. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1145/581630.581637 | CASES |
Keywords | Field | DocType |
custom hardware accelerator,subsequent physical synthesis,static timing analysis engine,predictable performance,present architecture synthesis result,high-level specification,multiple level,synthesizes minimal cost rt-level,cycle-time aware architecture synthesis,embedded application,validate useful operator chain,high level synthesis,timing analysis,cycle time,hardware architecture,clock frequency,static timing analysis,hardware accelerator | Computer science,Real-time computing,Operator (computer programming),Physical synthesis,Computer architecture,Architecture,Custom hardware,Parallel computing,High-level synthesis,Static timing analysis,Clock rate,Hardware architecture,Embedded system | Conference |
ISBN | Citations | PageRank |
1-58113-575-0 | 13 | 0.93 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mukund Sivaraman | 1 | 130 | 9.56 |
| Shail Aditya | 2 | 259 | 28.87 |