Name
Abstract | ||
|---|---|---|
This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of the dual MAC unit is identical to the result of the operations performed serially with saturation after each multiplication and each addition |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/GLSV.1999.757413 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
saturating adder,parallel saturating fractional arithmetic,dual mac unit,saturating mac operation,specialized saturation logic,single mac unit,cycle latency,digital signal processing,logic,circuits,parallel processing,speech,adders,gsm,arithmetic,decoding,mobile communication | Saturation (chemistry),Adder,Computer science,Parallel processing,Arithmetic logic unit,Arithmetic,Electronic engineering,Real-time computing,Multiplier (economics),Multiplication,Saturation arithmetic,Fold (higher-order function) | Conference |
ISSN | ISBN | Citations |
1066-1395 | 0-7695-0104-4 | 5 |
PageRank | References | Authors |
0.54 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Navindra Yadav | 1 | 76 | 3.65 |
| Michael Schulte | 2 | 54 | 8.18 |
| John Glossner | 3 | 141 | 22.12 |