Paper Info
Title
Performance Analysis of System Overheads in TCP/IP Workloads
Abstract
Current high-performance computer systems are unable to saturate the latest available high-bandwidth networks such as 10 Gigabit Ethernet. A key obstacle in achieving 10 gigabits per second is the high overhead of communication between the CPU and network interface controller (NIC), which typically resides on a standard I/O bus with high access latency. Using several network-intensive benchmarks, we investigate the impact of this overhead by analyzing the performance of hypothetical systems in which the NIC is more closely coupled to the CPU, including integration on the CPU die. We find that systems with high-latency NICs spend a significant amount of time in the device driver. NIC integration can substantially reduce this overhead, providing significant throughput benefits when other CPU processing is not a bottleneck. NIC integration also enables cache placement of DMA data. This feature has tremendous benefits when payloads are touched quickly, but potentially can harm performance in other situations due to cache pollution.
Year
DOI
Venue
2005
10.1109/PACT.2005.35
IEEE PACT
Keywords
Field
DocType
ip workloads,significant throughput benefit,high access latency,significant amount,cache placement,nic integration,high overhead,system overheads,cpu processing,o bus,gigabit ethernet,performance analysis,dma data,network interfaces,resource allocation,network interface controller,computer networks
Computer science,Cache,10 Gigabit Ethernet,Computer network,Real-time computing,Throughput,Network interface,Central processing unit,Computer performance,Cache pollution,Parallel computing,Network interface controller,Embedded system
Conference
ISBN
Citations 
PageRank 
0-7695-2429-X
19
1.19
References 
Authors
9
6
Name
Order
Citations
PageRank
Nathan Binkert188249.23
Lisa Hsu274640.78
Ali Saidi3155262.07
Ronald G. Dreslinski4125881.02
Andrew L. Schultz5191.19
Steven K. Reinhardt63885226.69