Name
Title | ||
|---|---|---|
Over 10-times high-speed, energy efficient 3D TSV-integrated hybrid ReRAM/MLC NAND SSD by intelligent data fragmentation suppression |
Abstract | ||
|---|---|---|
A 3D through-silicon-via (TSV)-integrated hybrid ReRAM/multi-level-cell (MLC) NAND solid-state drive's (SSD's) architecture is proposed with NAND-like interface (I/F) and sector-access overwrite policy for ReRAM. Furthermore, intelligent data management algorithms are proposed to suppress data fragmentation and excess usage of MLC NAND. As a result, 11-times performance increase, 6.9-times endurance enhancement and 93% write energy reduction are achieved. Both ReRAM write and read latency should be less than 3 μs to obtain these improvements. The required endurance for ReRAM is 105. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ASPDAC.2013.6509566 | ASP-DAC |
Keywords | Field | DocType |
nand circuits,endurance enhancement,random-access storage,write energy reduction,3d through-silicon-via-integrated hybrid reram/multi-level-cell nand solid-state drive architecture,three-dimensional integrated circuits,energy efficient 3d tsv-integrated hybrid reram/mlc nand ssd,reram write and read latency,intelligent data management algorithms,intelligent data fragmentation suppression,nand-like interface,sector-access overwrite policy,flash memories | Efficient energy use,Latency (engineering),Computer science,NAND gate,Fragmentation (computing),Real-time computing,Energy reduction,Computer hardware,Data management,Resistive random-access memory | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4673-3029-9 | 3 |
PageRank | References | Authors |
0.46 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chao Sun | 1 | 6 | 0.91 |
| Hiroki Fujii | 2 | 24 | 3.22 |
| Kousuke Miyaji | 3 | 59 | 9.73 |
| Koh Johguchi | 4 | 43 | 7.87 |
| Kazuhide Higuchi | 5 | 42 | 5.13 |
| Ken Takeuchi | 6 | 15 | 2.93 |