Paper Info
Title
High-Level Simulation of Embedded Systems: Experiences from the FIT Project
Abstract
This paper summarizes the experiences gained from, the EU project FIT which was aimed at the verification of TTP/C protocol. Several fault injection techniques have been successfully applied during the project, but we will focus mainly on the "high level simulation" approach. The key contribution of the paper is a summary of the lessons learned from our experiences with functional verification of embedded systems, using the discrete-time simulation method.
Year
DOI
Venue
2004
10.1109/ISORC.2004.1300363
SEVENTH IEEE INTERNATIONAL SYMPOSIUM ON OBJECT-ORIENTED REAL-TIME DISTRIBUTED COMPUTING, PROCEEDINGS
Keywords
Field
DocType
embedded computing,protocols,computational modeling,discrete time,embedded systems,embedded system,computer science,fault tolerance,formal verification,functional verification,formal specification,system testing,discrete event simulation
Functional verification,Computer science,Real-time computing,High level simulation,Fault injection,Distributed computing,Software engineering,System testing,Formal specification,Fault tolerance,Formal verification,Discrete event simulation,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
7
Authors
3
Name
Order
Citations
PageRank
Premysl Brada1253.01
Petr Grillinger21149.25
Stanislav Racek3144.98