Name
Abstract | ||
|---|---|---|
Presents an architecture for the efficient encoding of Reed-Solomon codes, with or without interleaving. This architecture utilizes a clock whose rate is r times the symbol rate, where r is the redundancy of the code. The finite field operations are performed in a sequential manner, requiring only one finite field multiplier and one finite field adder. All memory elements (except one symbol register) are consolidated into a discrete-time delay line, which can be easily implemented with a random access memory. This approach alleviates the clock skew problem and leads to significant hardware savings over the usual parallel approach, when the redundancy and/or interleaving depth are large. The architecture can be easily reconfigured for changes in the generator polynomial of the code, the amount of redundancy, and the interleaving depth |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/26.275291 | IEEE Transactions on Communications |
Keywords | Field | DocType |
generator polynomial,finite field multiplier,cmos integrated circuits,interleaving,reed solomon codes,discrete-time delay lines,codecs,parallel architectures,reed-solomon codes,random access memory,finite field operations,sequential encoding,encoding,architecture,symbol register,memory elements,finite field adder,clock skew problem,vlsi,redundancy,discrete time systems,delay lines,throughput,registers,galois fields,reed solomon code,clock skew,finite field,polynomials,gold,discrete time | Sequential logic,Adder,Computer science,Symbol rate,Polynomial code,Parallel computing,Electronic engineering,Reed–Solomon error correction,Redundancy (engineering),Clock skew,Interleaving | Journal |
Volume | Issue | ISSN |
42 | 1 | 0090-6778 |
Citations | PageRank | References |
1 | 0.35 | 2 |
Authors | ||
2 | ||