Title
Iteration bound analysis and throughput optimum architecture of SHA-256 (384,512) for hardware implementations
Abstract
The hash algorithm forms the basis of many popular cryptographic protocols and it is therefore important to find throughput optimal implementations. Though there have been numerous published papers proposing high throughput architectures, none of them have claimed to be optimal. In this paper, we perform iteration bound analysis on the SHA2 family of hash algorithms. Using this technique, we are able to both calculate the theoretical maximum throughput and determine the architecture that achieves this throughput. In addition to providing the throughput optimal architecture for SHA2, the techniques presented can also be used to analyze and design optimal architectures for some other iterative hash algorithms.
Year
DOI
Venue
2007
10.1007/978-3-540-77535-5_8
WISA
Keywords
Field
DocType
throughput optimal architecture,throughput optimum architecture,popular cryptographic protocol,high throughput architecture,hash algorithm,iterative hash algorithm,iteration bound analysis,numerous published paper,hardware implementation,sha2 family,design optimal architecture,throughput optimal implementation,theoretical maximum throughput,design optimization,high throughput
Architecture,Hardware implementations,Cryptographic protocol,Computer science,Parallel computing,Theoretical computer science,Implementation,Hash function,Throughput
Conference
Volume
ISSN
ISBN
4867
0302-9743
3-540-77534-X
Citations 
PageRank 
References 
9
1.05
9
Authors
3
Name
Order
Citations
PageRank
Yong Ki Lee117410.12
Herwin Chan2284.87
Ingrid Verbauwhede34650404.57