Name
Abstract | ||
|---|---|---|
A novel approach, called PGEN, is proposed to generate test patterns for resettable or nonresettable synchronous sequential circuits, PGEN contains two major routines, Sequential PODEM (S-PODEM) and a differential fault simulator. Given a fault, S-PODEM uses the concept of multiple time compression supported by a pulsating model, and generates a test vector in a single (yet compressed) time frame. Logic simulation (included in S-PODEM) is invoked to expand the single test vector into a test sequence. The single test vector generation methodology and logic simulation are well coordinated and significantly facilitate sequential circuit test generation, A modified version of differential fault simulation is also implemented and included in PGEN to cover other faults detected by the expanded test sequence. Experiments using computer simulation have been conducted, and results are quite satisfactory. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1155/1996/68463 | VLSI DESIGN |
Keywords | DocType | Volume |
resettable or nonresettable synchronous sequential circuits, PODEM and sequential PODEM or S-PODEM, pulsating test generation or PGEN, differential fault simulator, multiple time compression | Journal | 4 |
Issue | ISSN | Citations |
3 | 1065-514X | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wen-Ben Jone | 1 | 419 | 46.30 |
| Nigam Shah | 2 | 212 | 20.11 |
| Anita Gleason | 3 | 0 | 0.68 |
| Sunil R. Das | 4 | 187 | 187.91 |