Name
Abstract | ||
|---|---|---|
One way of dealing with transient faults that will affect theinterconnection network of future large-scale ChipMultiprocessor (CMP)systems is by extending the cache coherence protocol. Fault tolerance atthe level of the cache coherence protocol has been proven to achieve verylow performance overhead in absence of faults while being able to supportvery high fault rates. In this work, we compare two already proposed fault-tolerant cache coherence protocols in a common framework and present anew one based in the cache coherence protocol used in AMD Opteron processors.Also, we thoroughly evaluate the performance of the three protocols,show how to adjust the fault tolerance parameters of the protocols toachieve a desired level of fault tolerance andmeasure the overhead achievedto be able to support very high transient fault rates. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-540-89894-8_48 | HiPC |
Keywords | Field | DocType |
amd opteron processor,fault-tolerant cache coherence protocol,fault tolerance andmeasure,cache coherence protocol,verylow performance overhead,transient fault,fault tolerance parameter,high transient fault rate,high fault rate,fault tolerance atthe level,fault tolerant,energy conservation | MSI protocol,Cache invalidation,Cache,MESIF protocol,Computer science,Parallel computing,MESI protocol,Cache algorithms,Bus sniffing,Smart Cache,Embedded system,Distributed computing | Conference |
Citations | PageRank | References |
2 | 0.36 | 12 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ricardo Fernández-Pascual | 1 | 9 | 2.31 |
| J. M. García | 2 | 588 | 58.90 |
| M. E. Acacio | 3 | 419 | 41.45 |
| José Duato | 4 | 3481 | 294.85 |