Name
Abstract | ||
|---|---|---|
In this paper we address the problem of placement of standard cells tinder the constraints of minimizing the clock-skew. We propose a quadratic programming based methodology for placement that not only results in a area and timing wise good placement but also a supporting zero-skew clock routing tree. Under the clock-skew constraints, our method produces significant reduction in the cost of zero-skew clock routing tree. During placement, we are able to obtain significant speed-up due to variable reduction and constrains modification. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1109/ICCD.1998.727053 | ICCD |
Keywords | Field | DocType |
clock-skew constrained placement,quadratic program,very large scale integration,routing,vlsi,quadratic programming,clock skew,circuits | Computer science,Parallel computing,Placement,Real-time computing,Clock skew,Quadratic programming,Electronic circuit,Very-large-scale integration,Clock routing | Conference |
ISBN | Citations | PageRank |
0-8186-9099-2 | 5 | 0.60 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Natesan Venkateswaran | 1 | 84 | 7.70 |
| Dinesh Bhatia | 2 | 385 | 47.05 |