Paper Info
Title
Hardware Implementation of the Binary Method for Exponentiation in GF(2m)
Abstract
Exponentiation in finite or Galois fields, GF(2m), is abasic operation for several algorithms in areas such ascryptography, error-correction codes and digital signalprocessing. Nevertheless the involved calculations arevery time consuming, especially when they are performedby software. Due to performance and security reasons, itis often more convenient to implement cryptographicalgorithms by hardware. In order to overcome the well-knowndrawback of little or inexistent flexibilityassociated to traditional Application Specific IntegratedCircuits (ASIC) solutions, we propose an architectureusing Field Programmable Gate Arrays (FPGA). A cheapbut still flexible modular exponentiation can beimplemented using these devices. We provide the VHDLdescription of an architecture for exponentiation inGF(2m) based in the square-and-multiply method, calledbinary method, using two multipliers in parallelpreviously developed by ourselves. Our structure,compared with other designs reported earlier, introducesan important saving in hardware resources.
Year
DOI
Venue
2003
10.1109/ENC.2003.1232886
ENC
Keywords
Field
DocType
flexible modular exponentiation,Hardware Implementation,Galois field,hardware resource,arevery time consuming,exponentiation inGF,digital signalprocessing,square-and-multiply method,calledbinary method,architectureusing Field Programmable Gate,Binary Method,abasic operation
Digital signal processing,Computer science,Parallel computing,Field-programmable gate array,Application-specific integrated circuit,Theoretical computer science,VHDL,Computer hardware,Exponentiation,GF(2),Hardware description language,Modular exponentiation
Conference
ISBN
Citations 
PageRank 
0-7695-1915-6
3
0.37
References 
Authors
0
5
Name
Order
Citations
PageRank
Mario Alberto Garcia Martinez1162.82
Guillermo Morales Luna230.71
F. Rodríguez-Henríquez3363.57
Garcia Martinez, M.A.430.37
Morales Luna, G.530.37