Name
Abstract | ||
|---|---|---|
We present the architecture and practical VLSI implementation of a 4-Tb/s single-stage switch. It is based on a combined input- and crosspoint-queued structure with virtual output queuing at the ingress, which has the scalability of input-buffered switches and the performance of output-buffered switches. Our system handles the large fabric-internal transmission latency that results from packaging up to 256 line cards into multiple racks. We provide the justification for selecting this architecture and compare it with other current solutions. With an ASIC implementation, we show that a single-stage multi-terabit buffered crossbar approach is viable today. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/CONECT.2002.1039251 | Hot Interconnects |
Keywords | Field | DocType |
asic implementation,combined input,large round-trip time support,crossbar approach,single-stage switch,four-terabit single-stage packet switch,crosspoint-queued structure,single-stage multi-terabit,practical vlsi implementation,large fabric-internal transmission latency,current solution,input-buffered switch,round trip time,packet switching,scalability,cmos integrated circuits,vlsi,cmos technology,queueing theory,line cards,application specific integrated circuits,switches,bipartite graph,emulation | Line card,Computer science,Transmission delay,Computer network,Burst switching,Packet switching,Terabit,Very-large-scale integration,Crossbar switch,Scalability | Conference |
ISBN | Citations | PageRank |
0-7695-1650-5 | 12 | 1.16 |
References | Authors | |
8 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| F. Abel | 1 | 12 | 1.16 |
| C. Minkenberg | 2 | 29 | 3.05 |
| R. P. Luijten | 3 | 44 | 3.18 |
| M. Gusat | 4 | 68 | 5.81 |
| I. Iliadis | 5 | 269 | 26.31 |