Title
A Random Jitter RMS Estimation Technique for BIST Applications
Abstract
This paper describes a RMS value measurement technique for random jitter. A jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of the random jitter are used to charge or discharge a capacitor. The voltage at the capacitor, in turn, modulates the frequency of VCO having a current-starved inverter, and whose frequency difference from the OR operation and the AND operation is used in calculating the RMS value of the random jitter. Circuit-level simulations show the validity of the proposed technique for up to 20% peak-to-peak jitter in the clock even with process variations. The proposed technique can be applied to BIST solutions for random jitter measurement on a transmitted clock signal.
Year
DOI
Venue
2009
10.1109/ATS.2009.38
Asian Test Symposium
Keywords
Field
DocType
bist applications,transmitted clock signal,reference clock signal,random jitter rms estimation,proposed technique,rms value,jittery clock signal,random jitter measurement,frequency difference,random jitter,rms value measurement technique,peak-to-peak jitter,rms,charge,process variation,capacitor,jitter,frequency modulation,logic gates,capacitors,vco,discharge
Clock signal,Capacitor,Computer science,Control theory,Voltage,Pulse-width modulation,Electronic engineering,Voltage-controlled oscillator,Clock skew,Jitter,Frequency modulation
Conference
ISSN
Citations 
PageRank 
1081-7735
1
0.36
References 
Authors
13
3
Name
Order
Citations
PageRank
Jae Wook Lee1338.37
Ji Hwan Chun291.37
J. Abraham34905608.16