Name
Abstract | ||
|---|---|---|
Modern FPGAs are used to implement a wide range of circuits, many of which have coarse-grained and fine-grained components. The ever-increasing size of these circuits places great demand on CAD tools to synthesize circuits faster and without loss in quality. Synthesizing coarse-grained components onto fine-grained FPGA resources is inefficient, and past attempts to optimize FPGAs for word-oriented datapaths have met with limited success. This paper presents a CAD flow to fully compile Verilog into a configuration bitstream for a new type of FPGA with time-multiplexed coarse-grained resources. We demonstrate two approaches with gains of 61x and 42x in synthesis time on average compared to QuartusII, but due to time-multiplexing and current synthesis limitations we achieve circuit speeds of 14x and 8.5x slower on average. We show the tools can also trade density for maximum clock frequency. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1950413.1950441 | FPGA |
Keywords | Field | DocType |
modern fpgas,time-multiplexed coarse-grained element,cad framework,fine-grained component,cad tool,fine-grained fpga resource,synthesis time,current synthesis limitation,coarse-grained component,circuit speed,cad flow,time-multiplexed coarse-grained resource,design,performance,reconfigurable computing | CAD,Computer science,Parallel computing,Field-programmable gate array,Compiler,Real-time computing,Verilog,Electronic circuit,Bitstream,Clock rate,Reconfigurable computing | Conference |
Citations | PageRank | References |
10 | 0.74 | 21 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| David Grant | 1 | 15 | 1.59 |
| Chris Wang | 2 | 18 | 2.28 |
| Guy G.F. Lemieux | 3 | 53 | 5.06 |