Name
Abstract | ||
|---|---|---|
Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1007/BF00137569 | J. Electronic Testing |
Keywords | Field | DocType |
analog BIST,Built-In Self Test,Design For Testability,current and voltage self-testing,Built-In Voltage Sensor | Design for testing,Automatic test pattern generation,Analog multiplier,Analog device,Fault coverage,Computer science,Automatic test equipment,Electronic engineering,Field-programmable analog array,Test compression | Journal |
Volume | Issue | ISSN |
9 | 1-2 | 0923-8174 |
Citations | PageRank | References |
5 | 0.61 | 12 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christian Dufaza | 1 | 48 | 5.87 |
| Hassan Ihs | 2 | 20 | 2.35 |