Paper Info
Title
A Diagnostic Test Generation Procedure for Combinational Circuits Based on Test Elimination
Abstract
We propose a procedure for generating test patterns for diagnosis of combinational (or fully-scanned sequential) circuits based on stuck-at faults. The test generation procedure avoids the conventional fault-oriented test generation by observing that a test pattern to distinguish two faults can be obtained from a test pattern that detects both of the faults by changing the test pattern so as to "undetect" one of the faults, or change the primary outputs on which the faults are detected. The proposed procedure is applied starting from a fault detection test set (a test set that detects every detectable stuck-at fault). For every pair of faults left undistinguished by the test set, the procedure attempts to modify a test pattern that detects both faults such that the resulting, modified pattern would distinguish the faults. We present experimental results to demonstrate the numbers of fault pairs that can be distinguished by the proposed procedure assuming diagnosis based on full responses and diagnosis based on pass/fail information.
Year
DOI
Venue
1998
10.1109/ATS.1998.741661
Asian Test Symposium
Keywords
Field
DocType
test elimination,fault pair,detectable stuck-at fault,modified pattern,test generation procedure,proposed procedure,test set,diagnostic test generation procedure,procedure attempt,conventional fault-oriented test generation,test pattern,fault detection test set,combinational circuit,automatic test pattern generation,diagnostic test,fault detection,sequential circuits,sequential analysis,combinational circuits
Stuck-at fault,Automatic test pattern generation,Fault coverage,Fault detection and isolation,Computer science,Diagnostic test,Algorithm,Electronic engineering,Combinational logic,Electronic circuit,Test set
Conference
ISBN
Citations 
PageRank 
0-8186-8277-9
6
0.50
References 
Authors
6
2
Name
Order
Citations
PageRank
Irith Pomeranz13829336.84
W. Kent Fuchs21469279.02