Name
Title | ||
|---|---|---|
Reliability analysis of combinational circuits with the influences of noise and single-event transients |
Abstract | ||
|---|---|---|
Noise-immunity is an important design criterion with CMOS dimension scaling to nanometers. Furthermore, nanometer circuits devices are also more prone to soft errors induced by single event transients (SETs). In this work, we set up a model to analyze the reliability induced by both SETs and noise. We derive the constraints for the reliability enhancement of logic circuits for allowing design circuits with both better noise-immunity and higher tolerance to soft errors. Simulation combining Hspice and Matlab are given to verify the proposed constraints. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/DFT.2013.6653609 | DFT |
Keywords | Field | DocType |
logic circuits,spice,matlab,transients,hspice,integrated circuit reliability,combinational circuits,noise immunity,single-event transients,reliability analysis,mathematics computing,cmos logic circuits,integrated circuit noise,nanometer circuits,soft errors,cmos dimension scaling,radiation hardening (electronics) | Logic gate,Digital electronics,Logic optimization,Computer science,Electronic engineering,CMOS,Combinational logic,Mixed-signal integrated circuit,Integrated injection logic,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
1550-5774 | 978-1-4799-1583-5 | 0 |
PageRank | References | Authors |
0.34 | 11 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kaikai Liu | 1 | 190 | 20.37 |
| Hao Cai | 2 | 60 | 21.94 |
| Ting An | 3 | 5 | 3.52 |
| Lirida A. B. Naviner | 4 | 83 | 26.52 |
| Jean-François Naviner | 5 | 114 | 18.62 |
| Hervé Petit | 6 | 23 | 5.29 |