Name
Abstract | ||
|---|---|---|
In this paper we consider the problem of exploiting infeasible clock gating functions. Analysis of industrial designs reveals a large margin of potential for power saving based on clock gating functions that initially appear to be useless due to timing violation or excessive power consumption. We propose two optimization techniques for resurrecting such functions that can be used as a generic post-processing phase in an automatic clock gating tool. The first provides timing-aware approximation and the second aims at generating large gating domains by clustering similar clock gating functions. Our experimental results show that the combination of these two techniques yields an additional power saving of up to 78% in industrial designs. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1629911.1629957 | DAC |
Keywords | Field | DocType |
large gating domain,infeasible clock-gating function,infeasible clock,automatic clock,large margin,similar clock,industrial design,additional power saving,techniques yield,excessive power consumption,approximation,clock gating,energy efficiency,clustering algorithms,data structures,design optimization,clustering,integrated circuit design,chip scale packaging,boolean functions,functional analysis,logic gates,algorithm design and analysis | Boolean function,Data structure,Clock gating,Logic gate,Gating,Computer science,Electronic engineering,Real-time computing,Integrated circuit design,Cluster analysis,Power consumption | Conference |
ISSN | Citations | PageRank |
0738-100X | 15 | 1.03 |
References | Authors | |
12 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eli Arbel | 1 | 67 | 4.23 |
| Cindy Eisner | 2 | 484 | 38.78 |
| Oleg Rokhlenko | 3 | 250 | 17.03 |