Name
Abstract | ||
|---|---|---|
This paper presents a hardware architecture and its FPGA implementation for Real-Time operating systems support. Dedicated hardware units are responsible for the maintenance of a 32 tasks list organized by time priority. The co-processor also communicates with the microprocessor to program interrupt modes and tasks. This dedicated HW architecture was easily prototyped in modern FPGAs, being a cost-effective solution to free microcontrollers from the burden of tasks time management. The FPGA has been completely synthesized based on a HDL description, allowing its use as a macrocell in larger designs. Tasks resolution is of 100 mu s. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1109/EMWRTS.1997.613761 | NINTH EUROMICRO WORKSHOP ON REAL TIME SYSTEMS, PROCEEDINGS |
Keywords | Field | DocType |
high level synthesis,process control,job shop scheduling,computer architecture,logic design,real time operating systems,field programmable gate arrays,hardware description languages,operating systems,interrupts,coprocessors,microcontrollers,real time systems,real time operating system,hardware architecture,hardware,control systems,coprocessor,time management,automatic control,cost effectiveness | Interrupt,Computer science,High-level synthesis,Field-programmable gate array,Real-time computing,Real-time operating system,Microcontroller,Timer,Operating system,Hardware description language,Hardware architecture,Embedded system | Conference |
ISSN | Citations | PageRank |
1068-3070 | 0 | 0.34 |
References | Authors | |
1 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| A. Parisoto | 1 | 0 | 0.34 |
| A. Souza Jr. | 2 | 0 | 0.34 |
| Luigi Carro | 3 | 1393 | 166.42 |
| M. Pontremoli | 4 | 0 | 0.34 |
| C. Pereira | 5 | 0 | 0.68 |
| A. A. Suzim | 6 | 2 | 1.10 |