Name
Abstract | ||
|---|---|---|
Multiple-input multiple-output (MIMO) technique can significantly increase data throughput without sacrificing additional bandwidth. However, data detection at the receiver and its VLSI implementation is challenge due to high computation complexity. This paper presents the VLSI architecture and implementation for a 4x4 64-QAM soft-output K-Best MIMO detector. A novel deeply pipelined architecture which makes use of all the full-length ZF-augmented discarded paths (DPs) is designed to reduce complexity and improve BER performance. Furthermore, to save area and latency, two improvement methods-abandoning DPs of bottom levels and performing ZF-augmentation at the last stage are proposed. The presented detector improves the BER performance by 2.3dB at BER=10(-3) compared to the conventional soft K-Best scheme when using the minimum mean squared error-sorted QR decomposition (MMSE-SQRD). It can achieve a peak throughput of 855 Mbps while consuming 223K gates, 301pJ/bit and 102 cycles for latency in SMIC 0.13 mu m CMOS process. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6271905 | 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) |
Keywords | Field | DocType |
throughput,64 qam,quadrature amplitude modulation,mimo,cmos integrated circuits,very large scale integration,measurement,detectors,bit error rate | Computer science,MIMO,Electronic engineering,CMOS,Bandwidth (signal processing),Throughput,Detector,Very-large-scale integration,QR decomposition,Bit error rate | Conference |
Volume | Issue | ISSN |
null | null | 0271-4302 |
Citations | PageRank | References |
7 | 0.53 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chunhui Ju | 1 | 7 | 0.53 |
| Jun Ma | 2 | 93 | 9.42 |
| Chengzhi Tian | 3 | 7 | 0.53 |
| Guanghui He | 4 | 80 | 12.73 |