Paper Info
Title
A combined optimization method for tuning two-level memory hierarchy considering energy consumption
Abstract
Tuning cache hierarchies in platforms for embedded systems can significantly reduce energy consumption. In this paper we combined two optimization methods for tuning both instruction and data cache configurations in a two-level memory hierarchy, where both levels have separate instruction and data caches. This kind of hierarchy allows us to evaluate instruction and data caches branches separately, although previous approaches have applied the same method for both branches of the hierarchy. This work evaluates several methods intended for two-level hierarchies, and the results showed that when we combine different methods for each branch of the hierarchy, results can be improved. Experiments based on simulations were performed for 12 applications from the Mibench suite benchmark and the combined method achieved better efficiency in 60% of the evaluated cases compared with existing heuristics. The proposed solution is only 11% less economic in terms of energy consumption than optimal values and required, on average, 42 simulations to conclude optimization mechanism, representing only 9% of the design space.
Year
DOI
Venue
2011
10.1155/2011/620578
Eurasip Journal on Embedded Systems
Keywords
Field
DocType
data caches branch,data cache configuration,two-level hierarchy,energy consumption,two-level memory hierarchy,combined method,different method,data cache,combined optimization method,separate instruction,cache hierarchy
Design space,Cache hierarchy,Memory hierarchy,Suite,Computer science,Parallel computing,Real-time computing,Heuristics,Data cache,Hierarchy,Energy consumption
Journal
Volume
Issue
ISSN
2011,
1
1687-3963
Citations 
PageRank 
References 
2
0.36
10
Authors
2
Name
Order
Citations
PageRank
Abel Guilhermino Silva-Filho16212.94
F. R. Cordeiro2467.14