Name
Title | ||
|---|---|---|
Probability of correctness of processor-array outputs using periodic concurrent error detection. |
Abstract | ||
|---|---|---|
Processor arrays, featuring modularity, regular interconnection, and high parallelism, are well suited for VLSI/WSI implementation and specific applications with high computational requirements. Error detection and recovery are important for some applications of processor arrays. Concurrent error detection (CED) techniques, which check normal system operations, are designed to detect errors caused... |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/24.510816 | IEEE Transactions on Reliability |
Keywords | Field | DocType |
Error correction,Fault detection,Degradation,Fault tolerance,Parallel processing,Hardware,Costs,Error analysis,Very large scale integration,Computer applications | Processor array,Computer science,Parallel computing,Correctness,Error detection and correction,Fault tolerance,Probabilistic logic,Interconnection,Computer hardware,Very-large-scale integration,Modularity,Reliability engineering | Journal |
Volume | Issue | ISSN |
45 | 2 | 0018-9529 |
Citations | PageRank | References |
3 | 0.44 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| P. P. Chen | 1 | 3 | 0.44 |
| A. N. Mourad | 2 | 3 | 0.44 |
| W. Kent Fuchs | 3 | 1469 | 279.02 |