Name
Abstract | ||
|---|---|---|
By allowing the occurrence of infrequent timing errors and correcting them with rollback mechanisms, the so-called timing speculation (TS) technique can significantly improve circuit energy-efficiency and hence has become one of the most promising solutions to mitigate the ever-increasing variation effects in nanometer technologies. As timing error recovery incurs non-trivial performance/energy overhead, it is important to reshape the delay distribution of critical paths in timing-speculated circuits to minimize their timing error rates. Most existing TS optimization techniques achieve this objective with post-synthesis techniques such as gate sizing or body biasing. In this work, we propose to conduct logic synthesis for timing-speculated circuits from the ground up. Being able to manipulate circuit structures during logic optimization, the proposed solution is able to dramatically reduce circuit timing error rates and hence improve its throughput, as demonstrated with experimental results on various benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2429384.2429512 | ICCAD |
Keywords | Field | DocType |
optimisation,nontrivial performance/energy overhead,timing-speculated circuits,logic circuits,circuit structure,timing circuits,circuit energy-efficiency,gate sizing,body biasing,circuit timing error rate,rollback mechanisms,delay distribution,nanometer technologies,various benchmark circuit,so-called timing speculation,circuit structures,timing error rate,timing-speculated circuit,infrequent timing error,logic synthesis,timing error recovery,ts optimization,ever-increasing variation effects,infrequent timing errors,existing ts optimization technique,logic optimization,critical paths,optimization,throughput,logic gates,noc,load balancing,error probability | Delay calculation,Logic synthesis,Logic gate,Pass transistor logic,Computer science,Logic optimization,Electronic engineering,Real-time computing,Static timing analysis,Throughput,Electronic circuit | Conference |
ISSN | Citations | PageRank |
1092-3152 | 19 | 0.75 |
References | Authors | |
23 | 5 | |