Name
Title | ||
|---|---|---|
Bi-Directional Trajectory Tracking With Variable Block-Size Motion Estimation for Frame Rate Up-Convertor |
Abstract | ||
|---|---|---|
This paper presents bi-directional trajectory tracking with variable block-size motion estimation for frame rate up-conversion (FRUC) based on the algorithm/architecture co-exploration (AAC) design methodology. Due to concurrent exploration in both algorithm and architecture domains, the designed system requires fewer computations and lowers hardware cost, but is capable of enhancing the accuracy of motion vectors (MVs) by allowing MV refinement from coarse-grained to fine-grained. In addition, a method that uses multiple block candidates tracked by bi-directional MVs for interpolation is also presented to improve visual quality. Benefiting from AAC, we can extract architectural information at algorithmic design phase to determine the most feasible architecture; then, the proposed algorithm can be mapped onto target platform smoothly. The proposed FRUC system, which is capable of converting the frame rate from 60 fps up to 120 fps at full HD (1920 × 1080) resolution, was successfully implemented and verified on a field-programmable gate array. This FRUC system's performance has not only been shown to surpass state-of-art alternatives in algorithmic performance, but its hardware cost is less than the comparable works described in the literature. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/JETCAS.2014.2298923 | IEEE J. Emerg. Sel. Topics Circuits Syst. |
Keywords | Field | DocType |
algorithm domain,multiple-block candidates,bidirectional trajectory tracking,field-programmable gate array (fpga),interpolation,aac design methodology,frame rate up-convertor,motion estimation,architectural information,frame rate up-conversion (fruc),concurrent exploration,coarse-grained refinement,fine-grained refinement,fruc system,bi-directional mv,field-programmable gate array,variable block-size motion estimation,field programmable gate arrays,motion vector accuracy,algorithmic design phase,mv refinement,architecture domain,motion-compensated interpolation,algorithm-architecture co-exploration design methodology,visual quality,design methodology,algorithm design and analysis,field programmable gate array,trajectory,tracking | Block size,Algorithm design,Computer science,Interpolation,Field-programmable gate array,Real-time computing,Electronic engineering,Gate array,Frame rate,Motion estimation,Trajectory | Journal |
Volume | Issue | ISSN |
4 | 1 | 2156-3357 |
Citations | PageRank | References |
6 | 0.47 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gwo Giun Lee | 1 | 92 | 15.89 |
| Chun-Fu Chen | 2 | 46 | 9.08 |
| Ching-Jui Hsiao | 3 | 339 | 13.17 |
| Jui-Che Wu | 4 | 9 | 0.92 |