Name
Abstract | ||
|---|---|---|
It takes about four to five weeks to fabricate a semiconductor memory device. As the fabrication process consists of various operations, there is a possibility of fabricating a final product with defects. It would be impossible for us to repair a memory device if it has numerous defects that cannot be dealt with properly. However, in case of a small number of defects, it is desirable to reuse a defective die (standard unit measuring a device on a wafer) after repair rather than to discard it, because reuse is an essential element for memory device manufactures to cut costs effectively. To perform the reuse, laser-repair process and redundancy analysis for setting an accurate target in the laser-repair process is needed. In this paper, cost reduction was attempted by reducing time in carrying out a new type of redundancy analysis, after simulating each defect. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1007/978-3-540-30134-9_14 | Lecture Notes in Artificial Intelligence |
Keywords | Field | DocType |
cost effectiveness,semiconductor manufacturing | Wafer,Semiconductor memory,Spare part,Reuse,Computer science,Semiconductor device fabrication,Redundancy (engineering),Very-large-scale integration,Cost reduction,Reliability engineering | Conference |
Volume | ISSN | Citations |
3215 | 0302-9743 | 1 |
PageRank | References | Authors |
0.38 | 5 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Youngshin Han | 1 | 27 | 8.28 |
| Chil-Gee Lee | 2 | 47 | 16.85 |