Name
Title | ||
|---|---|---|
The effect of a post processing thermal anneal on pre-existing and stress induced electrically active defects in ultra-thin SiON dielectric layers |
Abstract | ||
|---|---|---|
In this work we demonstrate the effects of a post processing high temperature anneal on the reliability of ultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage current, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. The devices under consideration were annealed at several temperatures up to 500°C. We show that different mechanisms dominate the leakage behaviour at different temperatures by examining the relative leakage in the low voltage range. In particular for pmos devices, the emptying of electron traps induced by temperature and subsequent annealing of these traps alters the leakage current profiles significantly, dependent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown (TDDB) lifetimes of nmos devices and examine the reasons for this. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1016/j.microrel.2010.09.019 | Microelectronics Reliability |
Keywords | Field | DocType |
low voltage,leakage current,stress induced leakage current,thermal annealing | Leakage (electronics),Dielectric strength,NMOS logic,Dielectric,Time-dependent gate oxide breakdown,Electronic engineering,Annealing (metallurgy),Engineering,PMOS logic,SILC | Journal |
Volume | Issue | ISSN |
51 | 3 | 0026-2714 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert O’Connor | 1 | 0 | 1.01 |
| Greg Hughes | 2 | 0 | 1.01 |