Name
Abstract | ||
|---|---|---|
In this paper, we contributed a VLSI architecture design for H.264/AVC intra frame coder. First, analysis of coding algorithm is provided by using a RISC model to obtain the proper degrees of parallelism under SDTV specification. Second, a two-stage macroblock pipelining is proposed to double the processing capability and hardware utilization. Third, Hadamard-based mode decision is modified as DCT-based version to reduce the 40% of memory access. To sum up, our system architecture achieves 215 times of speed compared with RISC-based software implementation in terms of processing cycles. In addition, we also made a lot of efforts on developing area-speed efficient modules. Reconfigurable intra predictor generator can support all kinds of prediction modes. Parallel multi-transform has four times throughput of the serial one with little area overhead. CAVLC engine can efficiently provide coding information for the bitstream packer. A prototype chip was fabricated with TSMC 0.25 μm CMOS technology and is capable of encoding 720×480 4:2:0 30 Hz video in real time at the working frequency of 54 MHz. The transistor count is 429 K, and the core size is only 1.855×1.885 mm2. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ISCAS.2004.1329260 | ISCAS (2) |
Keywords | Field | DocType |
tsmc cmos technology,coding algorithm,two stage macroblock pipelining,cmos integrated circuits,hardware utilization,0.25 micron,hadamard based mode decision,reduced instruction set computing,dct based version,encoding,parallel multitransform,prototype chip,h.264/avc intra frame coder,discrete cosine transforms,system architecture,bitstream packer,hardware architecture design,54 mhz,hadamard transforms,vlsi,video coding,integrated circuit design,risc based software,reconfigurable intra predictor generator,processing cycles,cavlc engine,prediction modes,vlsi architecture design,sdtv specification,30 hz,pipeline processing,throughput,hardware,algorithm design and analysis,engines,cmos technology,chip,process capability,real time,very large scale integration,hardware architecture,computer architecture | Macroblock,Pipeline (computing),Context-adaptive variable-length coding,Computer science,Electronic engineering,Reduced instruction set computing,Bitstream,Very-large-scale integration,Hardware architecture,Encoding (memory) | Conference |
Volume | ISBN | Citations |
2 | 0-7803-8251-X | 15 |
PageRank | References | Authors |
2.69 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu-Wen Huang | 1 | 1116 | 114.02 |
| Bing-Yu Hsieh | 2 | 483 | 54.76 |
| Tung-Chien Chen | 3 | 791 | 78.22 |
| Liang-Gee Chen | 4 | 3637 | 383.22 |