Name
Title | ||
|---|---|---|
A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system |
Abstract | ||
|---|---|---|
A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, m... |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/4.924857 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Engines,Rendering (computer graphics),Random access memory,Reduced instruction set computing,Logic arrays,Bandwidth,CMOS logic circuits,Graphics,Two dimensional displays,Tree graphs | Journal | 36 |
Issue | ISSN | Citations |
6 | 0018-9200 | 7 |
PageRank | References | Authors |
1.48 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong-Ha Park | 1 | 41 | 5.95 |
| Seon-Ho Han | 2 | 27 | 3.57 |
| Junghwan Lee | 3 | 50 | 12.51 |
| Hoi-Jun Yoo | 4 | 1574 | 226.79 |