Name
Abstract | ||
|---|---|---|
Due to the increasing bandwidth demand for the network-on-chip (NoC), interconnection networks become a dominant source of energy consumption in systems-on-chip (SoCs) and chip multi processors (CMPs). Therefore, energy efficient NoC is key to a successful SoC development. This paper presents an overview of different techniques to achieve energy efficiency at the different levels of NoC design including: a) component level where dynamic voltage scaling (DVS) and dynamic link shutdown (DLS) techniques are reviewed; b) circuit level, e.g., voltage swinging of signals; c) architectural level, where specialised tools, such as Wattch and Orion are discussed. We also summarise research on thermal optimisation issues. To the best of our knowledge, this is the first survey of recent research results on the area. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1504/IJCNDS.2010.035560 | International Journal of Communication Networks and Distributed Systems |
Keywords | Field | DocType |
circuit level,different technique,different level,component level,energy consumption,efficient noc,dynamic link shutdown,on-chip network,architectural level,energy efficiency,noc design,dls,network on chip,noc | Dynamic voltage scaling,System on a chip,Telecommunications,Computer science,Efficient energy use,Network on a chip,Chip,Voltage regulation,Energy consumption,Embedded system,Distributed computing,Low-power electronics | Journal |
Volume | Issue | ISSN |
5 | 4 | 1754-3916 |
Citations | PageRank | References |
7 | 0.52 | 40 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masud Al Aziz | 1 | 7 | 0.52 |
| Samee Ullah Khan | 2 | 1605 | 81.01 |
| Thanasis Loukopoulos | 3 | 293 | 30.66 |
| Bouvry, Pascal | 4 | 706 | 51.54 |
| Hongxiang Li | 5 | 270 | 16.42 |
| Juan Li | 6 | 194 | 13.79 |