Paper Info
Title
A 220-Mm(2), Four- And Eight-Bank, 256-Mb Sdram With Single-Sided Stitched Wl Architecture
Abstract
A 220-mm(2), 256-Mb SDRAM has been fabricated in fully planarized 0.22-mu m CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-mu m WL pitch in limited space. An intraunit address increment pipeline scheme hating two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single-ended read-write-drive bus reduce the ICG current to similar to 90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns, This design also uses a selectable row domain and divided column redundancy scheme that repairs up to similar to 1400 faults/chip with only 8% chip overhead.
Year
DOI
Venue
1998
10.1109/4.726565
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Keywords
DocType
Volume
asymmetric block activation, divided column redundancy, DRAM, flexible test mode, frequency doubling test mode, intraunit address increment, memory, SDRAM, selectable redundancy, single-ended RWD, stitched WL architecture, trench cell, 256-Mb DRAM, 256-Mb SDRAM
Journal
33
Issue
ISSN
Citations 
11
0018-9200
4
PageRank 
References 
Authors
0.71
3
14
Name
Order
Citations
PageRank
T. Kirihata1143.59
M. Gall240.71
K. Hosokawa340.71
J.-M. Dortu440.71
Hing Wong5122.49
P. Pfefferi640.71
B. L. Ji725823.76
O. Weinfurtner893.40
J. k. Debros940.71
H. Terletzki1093.06
M. Selz1171.96
W. Ellis1240.71
M. R. Wordeman13418.82
O. Kiehl1440.71