Name
Abstract | ||
|---|---|---|
In this paper we present a novel scheduling algorithm for testing embedded core-based SoCs. Given test conflicts, power consumption limitation and top level test access mechanism (TAM) constraint, we handle the constrained scheduling in a unique way that adaptively assigns the cores in parallel to the TAMs with variable width and concurrently executes the test sets by dynamic test partitioning, thus reducing the test cost in terms of the overall test time. Through simulation, we show that up to 30% of SoC testing time reduction can be achieved by using our scheduling approach. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/VTEST.2003.1197663 | VTS |
Keywords | Field | DocType |
localized delay defect,dynamically varied tam,longesttestable path,resistive short,sucha delay test set,power constrained test scheduling,longest-path-per-wire testset,graph theory,scheduling,scheduling algorithm,system on chip,vlsi | Fixed-priority pre-emptive scheduling,Fair-share scheduling,Computer science,Parallel computing,Two-level scheduling,Real-time computing,Least slack time scheduling,Rate-monotonic scheduling,Earliest deadline first scheduling,Dynamic priority scheduling,Round-robin scheduling | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-1924-5 | 18 |
PageRank | References | Authors |
0.86 | 15 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dan Zhao | 1 | 188 | 15.29 |
| Shambhu J. Upadhyaya | 2 | 781 | 69.61 |