Name
Title | ||
|---|---|---|
A Low-Power Implementation of Asynchronous 8051 Employing Adaptive Pipeline Structure |
Abstract | ||
|---|---|---|
This paper presents a low-power implementation of the A8051 processor. It employs an adaptive pipeline structure that allows to skip a redundant stage operation and to combine with the neighboring empty stage. The processor has three features to reduce the power dissipation as well as to improve performance: multilooping control for multicycle instructions, branch predictor for unconditional branc... |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCSII.2008.921589 | IEEE Transactions on Circuits and Systems II: Express Briefs |
Keywords | Field | DocType |
Pipeline processing,Power dissipation,Delay,Clocks,Computer architecture,Energy consumption,Wire,Computer aided instruction,CMOS technology,Logic circuits | Asynchronous communication,Power analysis,Pipeline transport,Logic gate,System on a chip,Computer science,Microprocessor,Electronic engineering,Datasheet,Branch predictor | Journal |
Volume | Issue | ISSN |
55 | 7 | 1549-7747 |
Citations | PageRank | References |
2 | 0.38 | 11 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jehoon Lee | 1 | 37 | 9.61 |
| Young Hwan Kim | 2 | 181 | 37.11 |
| Kyoung-Rok Cho | 3 | 217 | 31.77 |