Name
Abstract | ||
|---|---|---|
New nanotechnology-based devices are being researched to replace CMOS devices in order to overcome CMOS technology's scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes two new circuit simulation approaches that can effectively simulate nanotechnology devices with uncertain input sources and negative differential resistance problem. A new tool called NanoSim-RTD is developed has ed on the proposed new simulation techniques. The experimental results show a speedup of 1.48-37.1 times when compared with existing simulators. Further, this paper demonstrates a new way to design delay-insensitive nanocircuits, and the designs can be verified by using NanoSim-RTD. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TCSI.2007.895529 | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS |
Keywords | Field | DocType |
asynchronous, bias-based, resonant tunneling devices, stepwise equivalent conductance | Quantum tunnelling,Asynchronous communication,CMOS,Electronic engineering,Integrated circuit design,Engineering,Chaotic,Electrical engineering,Scaling,Speedup | Journal |
Volume | Issue | ISSN |
54 | 6 | 1549-8328 |
Citations | PageRank | References |
4 | 0.49 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Janet Meiling Wang | 1 | 118 | 14.10 |
| Bharat Sukhwani | 2 | 228 | 15.95 |
| Uday Padmanabhan | 3 | 9 | 0.97 |
| Dongsheng Ma | 4 | 157 | 24.75 |
| Kartik Sinha | 5 | 4 | 0.49 |