Name
Title | ||
|---|---|---|
Itucome: Hcdfg-Based Incremental Tuning Hw/Sw Co-Design Methodology For Multi-Level Exploration |
Abstract | ||
|---|---|---|
In this paper we present an iTuCoMe methodology which concentrates on providing a brand-new codesign framework of high-performance SoC systems for multi-level exploration. The main motivation of this work is that a fine trade-off between abstraction levels, design models and implementation accuracy can be explored under the design cycle as small as possible at system level. The proposed framework has been realized by relative algorithms and tools to map and transform a system specification to a feasible RTL implementation solution with arbitrarily linked processors, IP cores and ASICs. To improve the speed of convergence and reduce the iterative numbers of turnaround, iTuCoMe employs an incremental method to divide design space into three layers: 1) adaptive granularity for HW/SW partitioning; 2) incremental tuning for communication architecture generation; and 3) interconnect-driven high-level re-synthesis with floorplanning. Finally, we evaluate the iTuCoMe design methodology through an illustrative case study on JPEG decoder application. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/CSCWD.2005.194320 | PROCEEDINGS OF THE NINTH INTERNATIONAL CONFERENCE ON COMPUTER SUPPORTED COOPERATIVE WORK IN DESIGN, VOLS 1 AND 2 |
Keywords | Field | DocType |
HW/SW co-design, System-on-a-Chip, incremental tuning, multi-level exploration | Computer architecture,System on a chip,Computer science,Application-specific integrated circuit,Design methods,JPEG,Granularity,Abstraction layer,System requirements specification,Floorplan | Conference |
Citations | PageRank | References |
2 | 0.41 | 4 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haili Wang | 1 | 17 | 4.48 |
| Jinian Bian | 2 | 175 | 31.31 |
| Qiang Wu | 3 | 17 | 2.31 |
| Yunfeng Wang | 4 | 309 | 31.38 |