Name
Title | ||
|---|---|---|
Steady State Thereto-Mechanical Stress Prediction For Large Vlsi Circuits Using Gds Method |
Abstract | ||
|---|---|---|
Silicon integrated sensors for thereto-mechanical stress measurement in VLSI (Very Large Scale Integration) has been studied extensively in recent years due to the increasing complexity of modern semiconductor devices. As chip size has increased continuously to accommodate more functions in modern integrated circuits (IC) technology, the stress induced in a chip from packaging combined with self heating becomes serious and may result in device degradation, circuit malfunction and even chip cracking. Additional thermally induced stresses can be produced from heat dissipated by high power density circuits during operation. In this paper, steady state thereto-mechanical stress predictions for large VLSI circuits using gradient direction sensor (GDS) method is presented. The GDS method has been studied and analyzed for their applicability as inverse engineering problem that are capable to detect the spatial thermo-mechanical stress. Then finite element technique (FEM) will be used to build models to validate local thermal peaks prediction by GDS method. In this way we will explore the possibilities to minimize the thermal peaks in the critical areas for BGA (Ball Grid Array) packaged WSI (Wafer Scale Integration) devices. Hence, several considerations guided our study for a judicious placement of different sensors cells. That will enable accurate chip spatial prediction and control of thereto-mechanical stress. Subsequently, alternative for heat sources placement or distribution that are capable in reducing level of thermo-mechanical stress will be developed. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/CCECE.2006.277423 | 2006 CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, VOLS 1-5 |
Keywords | Field | DocType |
VLSI, packaging, thereto-mechanical, stress analysis, heat transfer, finite element, gradient direction sensor (GDS) | Ball grid array,Wafer-level packaging,Computer science,Chip,Electronic engineering,Stress (mechanics),Very-large-scale integration,Chip-scale package,Integrated circuit,Wafer-scale integration | Conference |
ISSN | Citations | PageRank |
0840-7789 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammed Bougataya | 1 | 0 | 1.01 |
| Ahmed Lakhsasi | 2 | 2 | 1.42 |
| Daniel Massicotte | 3 | 0 | 0.34 |