Name
Title | ||
|---|---|---|
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISSCC.2011.5746308 | ISSCC |
Keywords | Field | DocType |
low latency,low power electronics,multiplexing,capacitance,error correction,registers,register file | Computer science,Memory data register,Wire speed,Microprocessor,Register file,Electronic engineering,Latency (engineering),Memory buffer register,Computer hardware,Electrical engineering,Memory architecture,Memory cell | Conference |
Citations | PageRank | References |
9 | 0.88 | 0 |
Authors | ||
14 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gary S. Ditlow | 1 | 126 | 85.32 |
| Robert K. Montoye | 2 | 184 | 48.84 |
| Salvatore N. Storino | 3 | 15 | 2.34 |
| Sherman M. Dance | 4 | 9 | 1.22 |
| Sebastian Ehrenreich | 5 | 47 | 10.64 |
| Bruce M. Fleischer | 6 | 64 | 14.83 |
| Thomas W. Fox | 7 | 11 | 1.30 |
| Kyle M. Holmes | 8 | 9 | 0.88 |
| Junichi Mihara | 9 | 9 | 0.88 |
| Yutaka Nakamura | 10 | 105 | 18.97 |
| Shohji Onishi | 11 | 9 | 0.88 |
| Robert Shearer | 12 | 11 | 1.62 |
| Dieter F. Wendel | 13 | 78 | 15.62 |
| Leland Chang | 14 | 80 | 9.47 |